All Quiet on the Blogging Front – and then there was IDF

Dick James

Things have been a bit quiet lately; not that there haven’t been topics worth commenting, just that work life has been really, really busy for all of us.

That hasn’t changed, but I’ve had a few days in California at the Custom Integrated Circuit Conference (CICC) where Chipworks presented on the state-of-the-art in reverse engineering, and the Intel Developer Forum (IDF), and they sparked a few thoughts.

I’ve never been to IDF before, and it overwhelms with the kind of high-tech hype that Intel, Apple and Microsoft are becoming famous for. Keynote speeches, big stage, lots of lights, fanfares worthy of a mediaeval monarch, as the CEOs come out to make the big announcements – these guys have been watching the Oscars! That’s not a strange parallel – they are paid as much as film stars these days!

Aside from all that, there are a couple of nuggets that came up; the Intel 45-nm parts will be released on November 12, and Intel have actually drawn ahead of their two-year cycle, since they are showing off 32-nm test SRAMs; if I remember rightly, the 45-nm SRAM announcement was in early 2006. So of course we’ll be looking for the 45-nm parts as soon as they’re out there!

Associated with the technical sessions is a Technology Showcase – lots of booths by Intel, but also associated companies big and small, from Microsoft to small focused companies like Siano (mobile TV chips) and Akustica (MEMS microphones).

Intel Research also had a big presence, there was a row of demonstrations showing off leading edge stuff like power management and improving the discrimination of wireless links – not just within the chip and board design, but actively monitoring the environment and compensating for the other activity that is going on. We live in a very noisy electromagnetic atmosphere these days, everything from microwave ovens to Bluetooth links and mobile/portable phones using multiple frequency bands, so it’s not surprising that there’s room for improvement.

The display that really caught my eye was part of their Terascale Computing program. It was a wafer of alternating (65-nm) SRAM and 80-core processor dice, and there was a working demo of the processor running at >1 – 2 teraflops, using 100-200W. It seems the target is to achieve teraflop computing at <100W, and on this evidence Intel has done it.

Figure 2: Future tera-scale chips will use an array of tens to hundreds of cores with reconfigurable caches, as well as special-purpose hardware accelerators (image from Intel Whitepaper)

This is very much still a proof-of-concept exercise – don’t expect to see these on the market any time soon! The 80 cores are dedicated floating-point processors, not Presler-type cores (the die would be huge!), and the exercise is to use these parts to experiment on topics such as data-path routing, power management using multiple cores, and the many other technical concerns there are.

There are some interesting features in the processor already, though; the cores are designed to be operated independently, and the physical routing layout is such that they can be grouped in multiple different ways. Each core has a six-way routing block, including out-of-plane – they are anticipating stacking the die with a memory chip at some point. In fact, the SRAM parts on the demo wafer were laid out to allow for through-silicon vias or face-to-face stacking with the processor die. I had not realized that Intel had been doing so much package development, but apparently their guys in Arizona have all the infrastructure to handle 70-micron-thick dice and stacked packaging – for them, it’s not how to do it, it’s when.

It also seems that each core has in-built temperature sensors, so that if a core gets too hot the power can be managed by lowering voltage or frequency, as is already used in today’s processors, but in this case it also allows core-swapping to switch the processing to another (cooler) core. Just one way of controlling power, since it could also be done by other techniques such as tweaking duty cycles, etc.

Terascale Computing is Intel’s largest R&D program, with ~250 people working on it globally, so definitely something to watch, and a pointer that the processor business is likely to go beyond the eight cores of the Cell processor by an order of magnitude or more. We’re already seeing the trend in specific applications such as graphics processing – the Nvidia G80 has 128 cores, but I gather that they are not usable for more generic applications.

One of the more eerie things about the forum was the RFID tags on our badges; we were tracked from room to room as we wandered around Moscone West. I’ve not been before, so I don’t know if this routine or not. This was used so that we could log on to the survey website for the sessions, and give our opinions – the website automatically listed the sessions attended so that we didn’t have to scroll through the long list of papers. A high-profile use of the RFID location was during the Thursday keynote – there was a draw for concert tickets, and the lucky winner was identified as being in the room, since we were all tracked going in there.

Most of the topics were user-oriented, so software, user environment (Internet, etc), and architecture, so way out my field as a process nerd. The keynotes are available in streaming video on the IDF website, but most of the presentations are passworded for attendees – but for a trip down memory lane watch the video of Gordon Moore, it’s a great reminder of how far the industry has come in the last forty years.

An interesting couple of days!